	
module hmc624_SPI(
input                 Reset,
input                  Sys_clk,
input     [5:0]     att_data,
output reg            SSEN,
output reg            SCK,
output reg            MOSI
);

////////////////////////////////////////////////////////////////////////
reg [5:0] att_data_reg;
reg start_spi_config;
always @(posedge Sys_clk) begin
    if(Reset)
        att_data_reg <= 6'b11_1111;
    else if(att_data_reg != att_data)
        att_data_reg <= att_data;
    else
        att_data_reg <= att_data_reg;
end

always @(posedge Sys_clk ) begin
    if(Reset)
        start_spi_config <= 1'b0;
    else if(start_spi_config == 1'b1)
        start_spi_config <= 1'b0;
    else if(att_data_reg != att_data)
        start_spi_config <= 1'b1;
    else 
        start_spi_config <= start_spi_config;
end
/////////////////////////////////////////////////////////////////////////
/*---------------------------------------------------------------------*/
reg SCK_d;

always @(posedge Sys_clk) begin
if(Reset) begin
    SCK_d     <= 0;
end
else begin
    SCK_d     <= SCK;
end
end

/////////////////////////////////////////////////////////////////////////
/*---------------------------------------------------------------------*/
localparam BAUD_RATE = 8;   // 10M/625Khz = 16
reg[15:0] SCK_Cnt;
reg start_p_d;

always @(posedge Sys_clk) begin
if(Reset) begin
    SCK         <= 1;
    SCK_Cnt     <= 0;
end
else if(SSEN==0) begin
    if(SCK_Cnt == BAUD_RATE) begin
        SCK     <= ~SCK;
        SCK_Cnt <= 0;
    end
    else begin
        SCK_Cnt <= SCK_Cnt + 1;
    end
end
else begin
    SCK         <= 1;
    SCK_Cnt     <= 0;
end
end



reg[15:0] SCK_Cnt2;
always @(posedge Sys_clk) begin
if(Reset) begin
    SSEN         <= 1;
    SCK_Cnt2     <= 0;
end
else if(start_spi_config) begin
    SSEN         <= 0;    
    SCK_Cnt2     <= 0;        
end
else if(SSEN==0) begin
    if({SCK_d,SCK} ==2'b10) begin 
        if(SCK_Cnt2==6) begin
            SCK_Cnt2 <= 0;
            SSEN      <= 1;
        end
        else begin
            SCK_Cnt2 <= SCK_Cnt2 + 1;
        end    
    end            
end
else begin
    SSEN         <= 1;
    SCK_Cnt2     <= 0;        
end
end

//===================================================================
//--TX
//===================================================================

reg[2:0]          COUNTER_txd_bit;
reg  [5:0] att_data_temp;
always @(posedge Sys_clk) begin
if(Reset) begin
    MOSI              <= 0;
    COUNTER_txd_bit <= 0;
end
else if(start_spi_config) begin
      att_data_temp<=att_data_reg;
    end
else if(SSEN==0) begin
    if({SCK_d,SCK} ==2'b10)  
    begin
         MOSI          <= att_data_temp[5];
        if(COUNTER_txd_bit==5) begin
            MOSI     <=0;
            COUNTER_txd_bit <= 0;
            att_data_temp<=att_data_reg;
            end
        else begin
            att_data_temp <= att_data_temp<<1;
            COUNTER_txd_bit <= COUNTER_txd_bit + 1;
        end    
    end
end
else begin
    MOSI             <= 0;
    COUNTER_txd_bit <= 0;
end
end
endmodule
